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version 4.2 september 2003 1/47 TDA9109A low-cost i 2 c controlled deflection processor for multisync monitor features general n sync processor n 12v supply voltage n 8v reference voltage n horizontal lock/unlock output n read/write i 2 c interface n vertical moire n b+ regulator - internal pwm generator for b+ current mode step-up converter - switchable to step-down converter -i 2 c adjustable b+ reference voltage - output pulses synchronized on horizontal frequency - internal maximum current limitation horizontal n self-adaptative n dual pll concept n 150khz maximum frequency n x-ray protection input n i 2 c controls: horizontal duty-cycle, h-position vertical n vertical ramp generator n 50 to 185hz agc loop n geometry tracking with vpos & vamp n i 2 c controls: vamp, vpos, s-corr, c-corr n dc breathing compensation i 2 c geometry corrections n vertical parabola generator (pin cushion - e/w, keystone, corner correction) n horizontal dynamic phase (side pin balance & parallelogram) n horizontal and vertical dynamic focus (horizontal focus amplitude, horizontal focus symmetry, vertical focus amplitude) description the TDA9109A is a monolithic integrated circuit assembled in a 32-pin shrink dual in line plastic package. this ic controls all the functions related to the horizontal and vertical deflection in multi- mode or multi-frequency computer display moni- tors. the internal sync processor, combined with the very powerful geometry correction block, make the TDA9109A suitable for very high performance monitors, using very few external components. the horizontal jitter level is very low. it is particu- larly well-suited to high-end 15" and 17" monitors. combined with the st7275 microcontroller family, tda9206 (video preamplifier) and stv942x (on- screen display controller), the TDA9109A allows fully i 2 c bus-controlled computer display monitors to be built with a reduced number of external com- ponents. ordering information ordering code package TDA9109A shrink 32 (plastic) 1
table of contents 3 2/47 pin connections 4 pin connections 5 quick reference data 6 block diagram 8 absolute maximum ratings 9 thermal data 9 i2c read/write 10 sync processor 10 horizontal section 11 vertical section 13 dynamic focus section 15 geometry control section 16 b+ section 18 typical output waveforms 20 i 2 c bus address table 24 i 2 c bus address table 25 operating description 27 1 general considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2i 2 c control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5sync processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6sync identification status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.7ic status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8sync inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.9sync processor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2 horizontal part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1internal input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2pll1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3pll2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5x-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6horizontal and vertical dynamic focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 vertical part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2i2c control adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3.3vertical moir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4basic equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5e/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6dynamic horizontal phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2
table of contents 3 3/47 4 dc/dc converter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1step-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2step-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3step-up and step-down mode comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 internal schematics 39 package mechanical data 46
TDA9109A 4/47 pin connections h/hvin vsyncin hlockout pll2c c0 r0 pll1f hposition hfocuscap focus-out hgnd hfly href comp regin i sense 5v sda scl v cc bout gnd hout xray ewout vout vcap vref vagccap vgnd breath b+gnd 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TDA9109A 5/47 pin connections pin name function 1 h/hvin ttl compatible horizontal sync input (separate or composite) 2 vsyncin ttl compatible vertical sync input (for separated h&v) 3 hlockout first pll lock/unlock output (0 v: unlocked - 5 v: locked) 4 pll2c second pll loop filter 5 c0 horizontal oscillator capacitor 6 r0 horizontal oscillator resistor 7 pll1f first pll loop filter 8 hposition horizontal position filter (capacitor to be connected to hgnd) 9 hfocuscap horizontal dynamic focus oscillator capacitor 10 focus out mixed horizontal and vertical dynamic focus output 11 hgnd horizontal section ground 12 hfly horizontal flyback input (positive polarity) 13 href horizontal section reference voltage (to be filtered) 14 comp b+ error amplifier output for frequency compensation and gain setting 15 regin regulation input of b+ control loop 16 i sense sensing of external b+ switching transistor current,or switch for step-down converter 17 b+gnd ground (related to b+ reference adjustment) 18 breath dc breathing input control (compensation of vertical amplitude against ehv variation) 19 vgnd vertical section ground 20 vagccap memory capacitor for automatic gain control loop in vertical ramp generator 21 v ref vertical section reference voltage (to be filtered) 22 vcap vertical sawtooth generator capacitor 23 vout vertical ramp output (with frequency independant amplitude and s or c corrections if any). it is mixed with vertical position voltage and vertical moir. 24 ewout pin cushion - e/w correction parabola output 25 xray x-ray protection input (with internal latch function) 26 hout horizontal drive output (npn open collector) 27 gnd general ground (referenced to v cc ) 28 bout b+ pwm regulator output 29 v cc supply voltage(12v typ) 30 scl i 2 c clock input 31 sda i 2 c data input 32 5v supply voltage (5v typ.)
TDA9109A 6/47 quick reference data parameter value unit horizontal frequency 15 to 150 khz autosynch frequency (for given r0 and c0. can be easily increased by application) 1 to 4.5 f0 horizontal sync polarity input yes polarity detection (on both horizontal and vertical sections) yes ttl composite sync yes lock/unlock identification (on both horizontal 1st pll and vertical section) yes i 2 c control for h-position 10 % xray protection yes i 2 c horizontal duty cycle adjustment 30 to 65 % i 2 c free running frequency adjustment no stand-by function yes dual polarity h-drive outputs no supply voltage monitoring yes pll1 inhibition possibility no blanking outputs no vertical frequency 35 to 200 hz vertical autosync (for 150nf on pin 22 and 470nf on pin 20) 50 to 185 hz vertical s-correction (optimized for super flat tube) yes vertical c-correction yes vertical amplitude adjustment yes dc breathing control on vertical amplitude yes vertical position adjustment yes east/west (e/w) parabola output (also known as pin cushion output) yes e/w correction amplitude adjustment yes keystone adjustment yes corner correction with amplitude adjustment yes internal dynamic horizontal phase control yes side pin balance amplitude adjustment yes parallelogram adjustment yes tracking of geometric corrections with vertical amplitude and position yes reference voltage (both on horizontal and vertical) yes dynamic focus (both horizontal and vertical) yes i 2 c horizontal dynamic focus amplitude adjustment yes i 2 c horizontal dynamic focus symmetry adjustment yes i 2 c vertical dynamic focus amplitude adjustment yes
TDA9109A 7/47 detection of input sync (biased from 5v alone) yes vertical moir yes controlled v-moir amplitude yes frequency generator for burn-in no fast i 2 c read/write 400 khz b+ regulation adjustable by i 2 cyes horizontal size control no parameter value unit
TDA9109A 8/47 block diagram pll1f position r0 c0 hfly pll2c hout 7865124 26 phase/frequency comparator h-phase (7bits) vco phase comparator phase shifter h-duty (7bits) hout buffer safety processor controller spin bal 7bits x 2 x paral 7bits b+ lock/unlock identification sync processor sync input select (1bit) geometry tracking vdfamp 7bits internal reference (7bits) 5v amp symmetry 2x7bits x 2 x 2 corner 7bits e/wpcc 7bits keyst. 7 bits x vertical moire cancel 7bits+on/off TDA9109A vsync vpos 7bits vamp 7bits 7 bits 7 bits vertical oscillator ramp generator s and c correction i 2 c interface h ref v ref 11 19 17 29 25 28 16 14 15 hgnd vgnd vcc xray bout i sense comp regin bgnd 10 9 24 focus hfocus- ewout 23 18 20 22 v out breath v agccap v cap 21 13 32 27 30 31 1 2 3 h/hvin v syncin hlockout sda scl gnd 5v href vref cap x 4 x 2 +
TDA9109A 9/47 absolute maximum ratings thermal data symbol parameter value unit v cc supply voltage (pin 29) 13.5 v v dd supply voltage (pin 32) 5.7 v v in max voltage on pin 4 pin 9 pin 5 pins 6, 7, 8, 14, 15, 16, 20, 22 pins 10, 18, 23, 24, 25, 26, 28 pins 1, 2, 3, 30, 31 4.0 5.5 6.4 8.0 v cc v dd v v v v v v vesd esd susceptibility human body model, 100pf discharge through 1.5k w eiaj norm, 200pf discharge through 0 w 2 300 kv v t stg storage temperature -40, +150 c t j junction temperature +150 c t oper operating temperature 0, +70 c symbol parameter value unit r th(j-a) max. junction-ambient thermal resistance 65 c/w
TDA9109A 10/47 i 2 c read/write electrical characteristics (v dd = 5v, t amb = 25c) note: 1 see also i 2 c bus address table. sync processor operating conditions (v dd = 5v, t amb = 25c) electrical characteristics (v dd = 5v, t amb = 25c) note: 2 t h is the horizontal period. symbol parameter test conditions min. typ. max. units i 2 c processor (see 1 ) fscl maximum clock frequency pin 30 400 khz tlow low period of the scl clock pin 30 1.3 m s thigh high period of the scl clock pin 30 0.6 m s vinth sda and scl input threshold pins 30, 31 2.2 v vack acknowledge output voltage on sda input with 3ma pin 31 0.4 v i 2 c leak leakage current into sda and scl with no logic supply v dd = 0 pins 30, 31 = 5 v 20 m a symbol parameter test conditions min. typ. max. units hsvr voltage on h/hvin input pin 1 0 5 v mind minimum horizontal input pulses du- ration pin 1 0.7 m s mduty maximum horizontal input signal duty cycle pin 1 25 % vsvr voltage on vsyncin pin 2 0 5 v vsw minimum vertical sync pulse width pin 2 5 m s vsmd maximum vertical sync input duty cy- cle pin 2 15 % vextm maximum vertical sync width on ttl h/vcomposite pin 1 750 m s symbol parameter test conditions min. typ. max. units vinth horizontal and vertical input logic level (pins 1, 2) high level low level 2.2 0.8 v v rin horizontal and vertical pull-up resis- tor pins 1, 2 250 k w voutt extracted vsync integration time (% of t h ) on h/v composite (see 2 ) c0 = 820pf 26 35 %
TDA9109A 11/47 horizontal section operating conditions electrical characteristics (v dd = 12v, t amb = 25c)) symbol parameter test conditions min. typ. max. units vco i 0max max current from pin 6 pin 6 1.5 ma f(max.) maximum oscillator frequency 150 khz output section i12m maximum input peak current pin 12 5 ma hoi horizontal drive output maximum current pin 26, sunk current 30 ma symbol parameter test conditions min. typ. max. units supply and reference voltages v cc supply voltage pin 29 10.8 12 13.2 v v dd supply voltage pin 32 4.5 5 5.5 v i cc supply current pin 29 50 ma i dd supply current pin 32 5 ma v ref-h horizontal reference voltage pin 13, i = -2ma 7.6 8.2 8.8 v v ref-v vertical reference voltage pin 21, i = -2ma 7.6 8.2 8.8 v i ref-h max. sourced current on v ref-h pin 13 5 ma i ref-v max. sourced current on v ref-v pin 21 5 ma 1st pll section hpoit delay time for detecting polarity change (see 3 ) pin 1 0.75 ms vvco vco control voltage (pin 7) v ref-h = 8.2v f o f h (max.) 1.4 6.4 v v vcog vco gain (pin 7) r 0 = 6.49k w , c 0 =820pf 15.9 khz/v hph horizontal phase adjustment (see 4 ) % of horizontal period 10 % vbmi vbtyp vbmax horizontal phase setting value (pin 8) (see 4 ) minimum value typical value maximum value sub-address 01 byte x1111111 byte x1000000 byte x0000000 2.9 3.5 4.2 v v v ipii1u ipii1l pll1 filter current charge pll1 is unlocked pll1 is locked 140 1 m a ma f o free running frequency r 0 = 6.49k w , c 0 = 820pf 22.8 khz dfo/dt free running frequency thermal drift (no drift on external components) (see 5 ) -150 ppm/ c cr pll1 capture range fh(min.) fh(max.) (see note 6) f o +0.5 4.5f o khz khz hunlock dc level pin 3 when pll1 is locked 5 v
TDA9109A 12/47 note: 3 this delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync. note: 4 see figure 10 for explanation of reference phase. note: 5 these parameters are not tested on each unit. they are measured during our internal qualification. note: 6 a larger range may be obtained by application. note: 7 hjit = 10 6 x (standard deviation/horizontal period) note: 8 duty cycle is the ratio between the output transistor off time and the period. the power transistor is controlled off when the output transistor is off. note: 9 initial condition for safe operation start up. 2nd pll section and horizontal output section fbth flyback input threshold voltage (pin 12) 0.65 0.75 v hjit horizontal jitter (see 7 ) at 31.4khz 70 ppm hdmin hdmax horizontal drive output duty-cycle (pin 26) (see 8 ) sub-address 00 byte x1111111 byte x0000000 (see 9 ) 30 65 % % xrayth x-ray protection input threshold voltage, pin 25, see figure 14 7.6 8.2 8.8 v vphi2 internal clamping levels on 2nd pll loop filter (pin 4) low level high level 1.6 4.2 v v vscinh threshold voltage to stop h-out, v- out, b-out and reset xray when v cc < vscinh (see figure14) pin 29 7.5 v hdvd horizontal drive output (low level) pin 26, i out = 30ma 0.4 v symbol parameter test conditions min. typ. max. units
TDA9109A 13/47 vertical section operating conditions electrical characteristics (v cc = 12v, t amb = 25c) symbol parameter test conditions min. typ. max. units outputs section r load minimum load for less than 1% verti- cal amplitude drift pin 20 65 m w symbol parameter test conditions min. typ. max. units vertical ramp section vrb voltage at ramp bottom point pin 22 2.1 v vrt voltage at ramp top point (with sync) pin 22 5.1 v vrtf voltage at ramp top point (without sync) pin 22 vrt- 0.1 v vstd vertical sawtooth discharge time pin 22, c 22 = 150nf 70 m s vfrf vertical free running frequency (see 11 ) c 22 = 150nf 100 hz asfr auto-sync frequency (see 12 )c 22 = 150nf 5% 50 185 hz rafd ramp amplitude drift versus frequency at maximum vertical amplitude (see 10 ) c 22 = 150nf 50hz< f < 185hz 200 ppm/ hz rlin ramp linearity on pin 22 (see 11 ) 2.5v < v 27 < 4.5v 0.5 % vpos vertical position adjustment voltage (pin 23 - vout mean value) sub address 06 byte 00000000 byte 01000000 byte 01111111 3.2 3.6 4.0 v v v vor vertical output voltage (peak-to-peak on pin 23) sub address 05 byte 10000000 byte 11000000 byte 11111111 2.15 3.0 3.9 v v v voi vertical output maximum current (pin 23) 5ma dvs max vertical s-correction amplitude (see 13 ) 0xxxxxxx inhibits s-corr 11111111 gives max s-corr sub address 07 byte 11111111 d v/v pp at tv/4 d v/v pp at 3tv/4 -3.5 3.5 % % ccorr vertical c-corr amplitude 0xxxxxxx inhibits c-corr sub address 08 d v/v pp at tv/2 byte 10000000 byte 11000000 byte 11111111 -3 0 3 % % % vmoire vertical moir sub address 0c byte 01x11111 6mv
TDA9109A 14/47 note: 10 these parameters are not tested on each unit. they are measured during our internal qualification procedure. note: 11 with register 07 at byte 0xxxxxxx (s correction is inhibited) and register 08 at byte 0xxxxxxx (c correction is inhibited), the vertical sawtooth has a linear shape. note: 12 this is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin22 and pin 20, and with a constant ramp amplitude. note: 13 tv is the vertical period. note: 14 when not used, the dc breathing control pin must be connected to 12v. breathing compensation brrang dc breathing voltage range (see 14 ) v 18 112v bradj vertical output variation versus dc breathing control (pin 23) v 18 > v ref-v 1v TDA9109A 15/47 dynamic focus section electrical characteristics (v cc = 12v, t amb = 25c) note: 15 these parameters are not tested on each unit. they are measured during our internal qualification. note: 16 s and c correction are inhibited so the vertical output sawtooth has a linear shape. symbol parameter test conditions min. typ. max. units horizontal dynamic focus function hdfst horizontal dynamic focus sawtooth minimum level maximum level pin 9, capacitor on hfocuscap and c0 = 820pf, t h = 20 m s 2.2 4.9 v v hdfdis horizontal dynamic focus sawtooth discharge width start by hdfstart 400 ns hdfstart internal fixed phase advance versus hfly middle independent of frequency 1 m s hdfdc bottom dc output level r load = 10k w , pin 10 2.1 v tdfhd dc output voltage thermal drift (see 15 ) 200 ppm/ c hdfamp horizontal dynamic focus amplitude min byte xxx11111 typ byte xxx10000 max byte xxx00000 sub-address 03, pin 10, fh = 50khz, symmetric wave form 1 1.5 3.5 v pp v pp v pp hdfkeyst horizontal dynamic focus position advance for byte xxx11111 delay for byte xxx00000 sub-address 04 for time reference see figure 15 16 16 % % vertical dynamic focus function (positive parabola) ampvdf vertical dynamic focus parabola (added to horizontal) amplitude with vamp and vpos typical min. byte xx000000 typ. byte xx100000 max. byte xx111111 sub-address 0f 0 0.5 1 v pp v pp v pp vdfamp parabola amplitude function of vamp (tracking between vamp and vdf) with vpos typ. (see figure 1 and 16 ) sub-address 05 byte x0000000 byte x1000000 byte x1111111 0.6 1 1.5 v pp v pp v pp vhdfkeyt parabola asymmetry function of vpos control (tracking between vpos and vdf) with vamp max. a/b ratio b/a ratio sub-address 06 byte x0000000 byte x1111111 0.52 0.52
TDA9109A 16/47 geometry control section electrical characteristics (v cc = 12v, t amb = 25c) symbol parameter test conditions min. typ. max. units east/west e/w function ew dc dc output voltage with: - typical vpos - keystone inhibited pin 24, see figure 2 2.5 v tdew dc dc output voltage thermal drift see 15 100 ppm/ c ewpara parabola amplitude with: - max. vamp, - typ. vpos, - keystone and corner inhibited subaddress 0a byte 11111111 byte 11000000 byte 10000000 2.5 1.25 0 v pp v pp v pp ewtrack parabola amplitude function of vamp control (tracking between vamp and e/w) with: - typ. vpos, - typ. e/w amplitude, - corner and keystone inhibited ( 17 ) subaddress 05 byte 10000000 byte 11000000 byte 11111111 0.45 0.80 1.45 v pp v pp v pp keyadj keystone adjustment capability with: - - typ. vpos, - e/w inhibited, - corner inhibited and - max. vertical amplitude (see 17 and figure 4) subaddress 09 byte 10000000 byte 11111111 1 1 v pp v pp ew corner corner adjustment capability with: - typ. vpos, - e/w inhibited, - keystone inhibited - max. vertical amplitude subaddress 10 byte 11111111 byte 11000000 byte 10000000 + 3 0 - 3 v pp v pp v pp keytrack intrinsic keystone function of vpos control (tracking between vpos and e/w) with: - max. e/w amplitude - max. vertical amplitude a/b ratio b/a ratio subaddress 06 byte 00000000 byte 01111111 0.52 0.52
TDA9109A 17/47 note: 17 with register 07 at byte 0xxxxxxx (s correction is inhibited) and register 08 at byte 0xxxxxxx (c correction is inhibited), the vertical sawtooth has a linear shape. note: 18 t h is the horizontal period. note: 19 when not used, the dc breathing control pin must be connected to 12v. internal dynamic horizontal phase control spbpara side pin balance parabola amplitude (figure 3) with: - max. vamp, - typ. vpos - parallelogram inhibited (see 17 & 19 ) subaddress 0d byte 11111111 byte 10000000 +2.8 -2.8 %t h %t h spbtrack side pin balance parabola amplitude function of vamp control (tracking be- tween vamp and spb) with - max. spb, - typ. vpos - parallelogram inhibited (see 17 & 19 ) subaddress 05 byte 10000000 byte 11000000 byte 11111111 1 1.8 2.8 %t h %t h %t h paradj parallelogram adjustment capability with: - max. vamp, - typ. vpos - max. spb (see 17 & 19 ) subaddress 0e byte 11111111 byte 11000000 +2.8 -2.8 %t h %t h partrack intrinsic parallelogram function of vpos control (tracking between vpos and dhpc) with: - max. vamp, - max. spb - parallelogram inhibited (see 17 & 19 ) a/b ratio b/a ratio subaddress 06 byte x0000000 byte x1111111 0.52 0.52 symbol parameter test conditions min. typ. max. units
TDA9109A 18/47 b+ section operating conditions electrical characteristics (v cc = 12v, t amb = 25c) note: 20 0.5ma are sunk when b+ section is disabled. the purpose is to discharge the soft-start capacitor. note: 21 the external power transistor is off during 400ns of the hfocuscap discharge symbol parameter test conditions min. typ. max. units feedres minimum feedback resistor resistor between pins 15 and 14 5k w symbol parameter test conditions min. typ. max. units olg error amplifier open loop gain at low frequency ( 15 )85 db ugbw unity gain bandwidth (see 15 )6mhz iri regulation input bias current current sourced by pin 15 (pnp base) 0.2 m a eaoi error amplifier output current current sourced by pin 14 current sunk by pin 14 (see 20 ) 2 1.4 ma ma csg current sense input voltage gain pin 16 3 mceth max current sense input threshold voltage pin 16 1.3 v isi current sense input bias current current sunk by pin 16 (pnp base) 1 m a tonmax maximum on time of the external power transistor % of horizontal period f o = 27khz (see 21 ) 100 % b+osv b+output saturation voltage v 28 with i 28 = 10ma 0.25 v iv ref internal reference voltage on error amp (+) input for subaddress ob byte 1000000 5v v refadj internal reference voltage adjustment range byte 01111111 byte 00000000 +20 -20 % % pwmsel threshold for step-up/step-down selection pin 16 6 v t fb+ fall time pin 28 100 ns
TDA9109A 19/47 figure 1. vertical dynamic focus function figure 2. e/w output figure 3. dynamic horizontal phase control output figure 4. keystone effect on e/w output (pcc inhibited)
TDA9109A 20/47 typical output waveforms function sub address pin byte specification effect on screen vertical size 05 23 10000000 11111111 vertical position dc con- trol 06 23 00000000 v outdc = 3.2v 01000000 v outdc = 3.6v 01111111 v outdc = 4.0v vertical s linearity 07 23 0xxxxxxx: inhibited 11111111 =
TDA9109A 21/47 vertical c linearity 08 23 0xxxxxxx : inhibited 10000000 11111111 horizon- tal dynamic focus with: ampli- tude 03 10 x000 0000 x111 1111 - -- horizon- tal dynamic focus with: symme- try 04 10 x000 0000 x111 1111 - -- function sub address pin byte specification effect on screen = -3% =+3%
TDA9109A 22/47 keystone (trape- zoid) control 09 24 (e/w + cor- ner inhibited) 10000000 11111111 e/w (pin cushion) control 0a 24 (keystone + corner inhibited) 10000000 11111111 corner control 10 24 (keystone+e/w inhibited) 11111111 10000000 parallel- ogram control 0e (spb inhibited) 10000000 11111111 function sub address pin byte specification effect on screen 0.4v ew dc 0.4v ew dc ew dc 0v ew dc 1.4v 1.25v ew dc ew dc 1.25v internal 2.8% t h 2.8% t h
TDA9109A 23/47 side pin balance control 0d (parallelogram inhibited) 10000000 11111111 vertical dynamic focus with horizon- tal 0f 10 x111 1111 x000 0000 --- function sub address pin byte specification effect on screen internal 2.8% t h 2.8% t h
TDA9109A 24/47 i 2 c bus address table slave address (8c): write mode sub address definition slave address (8d): read mode no sub address needed. d8 d7 d6 d5 d4 d3 d2 d1 000000000horizontal d rive selection/horizontal duty cycle 100000001x-ray reset/horizontal po sition 200000000 3 0 - - 1 0 0 1 1 sync. priority/horizontal focus amplitude 4 0 - - 1 0 1 0 0 refresh/horizontal focus keystone 500000101vertical ramp amplitude 600000110vertical pos ition adjustment 700000111s correction 800001000c correction 900001001e/w keystone a00001010e/w amp litude b00001011b+ reference adjustment c00001000vertical moir d00001001side pin balance e00001010parallelogram f00001011vertical dynamic focus amp litude 1000010000e/w corner
TDA9109A 25/47 i 2 c bus address table d8 d7 d6 d5 d4 d3 d2 d1 write mode 00 [hdrive 0, off [1], on0] [0] horizontal duty cycle [0] [0] [0] [0] [0] 01 xray 1, reset [0] horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0] 02 03 sync 0, comp [1], sep horizontal focus amplitude [1] [0] [0] [0] [0] 04 detect refresh [0], off horizontal focus time position [1] [0] [0] [0] [0] 05 vramp 0, off [1], on vertical ramp amplitude adjustment [1] [0] [0] [0] [0] [0] [0] 06 vertical position adjustment [1] [0] [0] [0] [0] [0] [0] 07 s select 1, on [0] s correction [1] [0] [0] [0] [0] [0] 08 c select 1, on [0] c correction [1] [0] [0] [0] [0] [0] 09 e/w key 0, off [1] e/w keystone [1] [0] [0] [0] [0] [0] 0a e/w sel 0, off [1] e/w amplitude [1] [0] [0] [0] [0] [0] [0] 0b test h 1, on [0], off b + reference adjustment [1] [0] [0] [0] [0] [0] [0] 0c test v 1, on [0], off moir 1, on [0] vertical moir [0] [0] [0] [0] [0] 0d spb sel 0, off [1] side pin balance [1] [0] [0] [0] [0] [0] 0e parallelo 0, off [1] parallelogram [1] [0] [0] [0] [0] [0]
TDA9109A 26/47 [x] initial value data is transferred with vertical sawtooth retrace. we recommend setting the unspecified bit to [0] in order to ensure compatibility with future devices. 0f eq. pulse 1, on [0], off vertical dynamic focus amplitude [1] [0] [0] [0] [0] [0] 10 corner 1, on [0], off corner amplitude adjustment [1] [0] [0] [0] [0] [0] read mode hlock 0, on [1], no vlock 0, on [1], no xray 1, on [0], off polarity detection sync detection h/v pol [1], nega- tive v pol [1], nega- tive vext det [0], no det h/v det [0], no det v det [0], no det d8 d7 d6 d5 d4 d3 d2 d1
TDA9109A 27/47 operating description 1 general considerations 1.1 power supply the typical values of the power supply voltages v cc and v dd are 12 v and 5 v respectively. opti- mum operation is obtained for v cc between 10.8 and 13.2 v and v dd between 4.5 and 5.5 v. in order to avoid erratic operation of the circuit dur- ing the transient phase of vcc switching on, or off, the value of v cc is monitored: if v cc is less than 7.5 v typ., the outputs of the circuit are inhibited. similarly, before v dd reaches 4 v, all the i 2 c reg- ister are reset to their default value (see i 2 c con- trol table). in order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value: 8.2 v). two of these volt- age references are externally accessible, one for the vertical and one for the horizontal part. they can be used to bias external circuitry (if i load is less than 5 ma). it is necessary to filter the voltage references by external capacitors connected to ground, in order to minimize the noise and conse- quently the jitter on vertical and horizontal output signals. 1.2 i 2 c control TDA9109A belongs to the i 2 c controlled device family. instead of being controlled by dc voltages on dedicated control pins, each adjustment can be done via the i 2 c interface. the i 2 c bus is a serial bus with a clock and a data input. the general function and the bus protocol are specified in the philips-bus data sheets. the interface (data and clock) is a comparator whose threshold is 2.2 v with a 5 v supply. spikes of up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 400 khz. the data line (sda) can be used bidirectionally. in read-mode the ic sends reply information (1 byte) to the micro-processor. the bus protocol prescribes a full-byte transmis- sion in all cases. the first byte after the start con- dition is used to transmit the ic-address (hexa 8c for write, 8d for read). 1.3 write mode in write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the corre- sponding data byte. it is possible to send more than one data byte to the ic. if after the third byte no stop or start condition is detected, the circuit in- crements automatically by one the momentary subaddress in the subaddress counter (auto-incre- ment mode). so it is possible to transmit immedi- ately the following data bytes without sending the ic address or subaddress. this can be useful to reinitialize all the controls very quickly (flash man- ner). this procedure can be finished by a stop con- dition. the circuit has 18 adjustment capabilities: 3 for the horizontal part, 4 for the vertical, 3 for the e/w correction, 2 for the dynamic horizontal phase control, 2 for the vertical and horizontal moir op- tions, 3 for the horizontal and the vertical dynamic focus and 1 for the b+ reference adjustment. 18 bits are also dedicated to several controls (on/ off, horizontal forced frequency, sync priority, detection refresh and xray reset). 1.4 read mode during the read mode the second byte transmits the reply information. the reply byte contains the horizontal and vertical lock/unlock status, the xray activation status and, the horizontal and vertical polarity detection. it also contains the sync detection status which is used by the mcu to assign the sync priority. a stop condition always stops all the activities of the bus decoder and switches to high impedance both the data and clock line (sda and scl). see i 2 c subaddress and control tables. 1.5 sync processor the internal sync processor allows the TDA9109A to accept: ? separated horizontal & vertical ttl- compatible sync signal ? composite horizontal & vertical ttl- compatible sync signal
TDA9109A 28/47 1.6 sync identification status the mcu can read (address read mode: 8d) the status register via the i 2 c bus, and then select the sync priority depending on this status. among other data this register indicates the pres- ence of sync pulses on h/hvin, vsyncin and (when 12 v is supplied) whether a vext has been extracted from h/hvin. both horizontal and verti- cal sync are detected even if only 5 v is supplied. in order to choose the right sync priority the mcu may proceed as follows (see i 2 c address table): ? refresh the status register ? wait at least for 20ms (max. vertical period) ? read this status register sync priority choice should be: of course, when the choice is made, we can re- fresh the sync detections and verify that the ex- tracted vsync is present and that no sync type change has occurred. the sync processor also gives sync polarity information. 1.7 ic status the ic can inform the mcu about the 1st horizon- tal pll and vertical section status (locked or not) and about the xray protection (activated or not).resetting the xray internal latch can be done either by decreasing the v cc supply or di- rectly resetting it via the i 2 c interface. 1.8 sync inputs both h/hvin and vsyncin inputs are ttl com- patible triggers with hysteresis to avoid erratic de- tection. both inputs include a pull up resistor con- nected to v dd . 1.9 sync processor output the sync processor indicates on the d8 bit of the status register whether 1st pll is locked to an in- coming horizontal sync. its level goes to low when locked. this information is also available on pin 3 when sub-address 02 d8 is equal to 1. when pll1 is unlocked, pin 3 output voltage goes to 5v. 2 horizontal part 2.1 internal input conditions a digital signal (horizontal sync pulse or ttl com- posite) is sent by the sync processor to the hori- zontal input. it may be positive or negative (see figure 5). using internal integration, both signals are recog- nized if z/t < 25%. synchronization occurs on the leading edge of the internal sync signal. the minimum value of z is 0.7 m s. another integration is able to extract the vertical pulse from composite sync if the duty cycle is high- er than 25% (typically d = 35%), (see figure 6). vextd et hv det v det sync priority subaddress 03 (d8) comment sync type no yes yes 1 separated h&v yes yes no 0 composite ttl h&v
TDA9109A 29/47 figure 5. figure 6. the last feature performed is the removal of equal- ization pulses to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or extraneous pulses). this last feature is switched on/off by sub-address 0f d8. by default [0], equalization pulses will not be removed. 2.2 pll1 the pll1 consists of a phase comparator, an ex- ternal filter and a voltage-controlled oscillator (vco).the phase comparator is a phase frequen- cy type designed in cmos technology. this kind of phase detector avoids locking on wrong fre- quencies. it is followed by a charge pump, com- posed of two current sources : sunk and sourced (typically i =1 ma when locked and i = 140 m a when unlocked). this difference between lock/un- lock allows smooth catching of the horizontal fre- quency by pll1. this effect is reinforced by an in- ternal original slow down system when pll1 is locked, avoiding the horizontal frequency chang- ing too quickly. the dynamic behavior of pll1 is fixed by an external filter which integrates the cur- rent of the charge pump. a crc filter is generally used (see figure 7) figure 7. w 7 4 .7 m f pll1f 10nf 1.8k
TDA9109A 30/47 the pll1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator. inhibition is obtained by stopping high and low signals at the entry of the charge pump block (see figure 8). figure 8. figure 9. the vco uses an external rc network. it delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current propor- tional to the current in the resistor. the typical thresholds of the sawtooth are 1.6 v and 6.4 v. the control voltage of the vco is between 1.4 v and 6.4 v (see figure 9). the theoretical frequen- cy range of this vco is in the ratio of 1 to 4.5. the effective frequency range has to be smaller (1 to 4.2) due to clamp intervention on the filter lowest value. the sync frequency must always be higher than the free running frequency. for example, when us- ing a sync range between 24.8 khz and 100 khz, the suggested free running frequency is 23 khz. pll1 ensures the coincidence between the lead- ing edge of the sync signal and a phase reference obtained by comparison between the sawtooth of the vco and an internal dc voltage which is i 2 c adjustable between 2.9 v and 4.2 v (correspond- ing to 10 %) (see figure 10).
TDA9109A 31/47 the TDA9109A also includes a lock/unlock iden- tification block which senses in real time whether pll1 is locked or not on the incoming horizontal sync signal. the lock/unlock information is available through the i 2 c read and the pin 3 voltage level pll1 timing diagram figure 10. 2.3 pll2 pll2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the vco, taking into account the saturation time ts (see figure 11) figure 11. pll2 timing diagram the phase comparator of pll2 (phase type com- parator) is followed by a charge pump (typical out- put current: 0.5 ma). the flyback input consists of an npn transistor. this input must be current driven. the maximum recommended input current is 5 ma (see figure 12). figure 12. flyback input electrical diagram the duty cycle is adjustable through i 2 c from 30 % to 65 %. for a safe start-up operation, the initial duty cycle (after power-on reset) is 65% in order to avoid having too long a conduction period of the horizontal scanning transistor. the maximum storage time (ts max.) is (0.44t h - t fly /2). typically, t fly /t h is around 20 % which means that ts max is around 34 % of t h . the pll1 ensures the exact coincidence between the signal phase ref and hsync. a 10% t h phase adjustment is possible around the 3.4v point. phase ref1 is obtained by comparison between the sawtooth and a dc voltage adjustable between 2.9 v and 4.2 v. ho sc sawtooth 7/8 t h 1/8 t h 6.4v ref. for h position vb (2.9v TDA9109A 32/47 2.4 output section the h-drive signal is sent to the output through a shaping stage which also controls the h-drive duty cycle (i 2 c adjustable) (see figure 11). in order to secure the scanning power part operation, the out- put is inhibited in the following cases: ? when v cc or v dd are too low ? when the xray protection is activated ? during the horizontal flyback ? when the hdrive i 2 c bit control is off the output stage consists of a npn bipolar tran- sistor. only the collector is accessible (see figure 13 ). figure 13. this output stage is intended for reverse base control, where setting the output npn in off-state will control the power scanning transistor in off- state. the maximum output current is 30ma, and the corresponding voltage drop of the output v cesat is 0.4v max. obviously the power scanning transistor cannot be directly driven by the integrated circuit. an inter- face has to be added between the circuit and the power transistor either of bipolar or mos type. 2.5 x-ray protection the x-ray protection is activated by application of a high level on the x-ray input (8.2v on pin 25). it inhibits the h-drive and b+ outputs. this activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). this protection is latched; it may be reset either by v cc switch off or by i 2 c (see figure 14 ). figure 14. safety functions block diagram
TDA9109A 33/47 2.6 horizontal and vertical dynamic focus the TDA9109A delivers a horizontal parabola which is added on a vertical parabola waveform on pin 10. this horizontal parabola comes from a sawtooth in phase advance with flyback pulse mid- dle. the time advance versus horizontal flyback middle is kept constant versus frequency (about 1 m s). symmetry and amplitude are i 2 c adjustable (see figure 15). the vertical dynamic focus is tracked with vpos and vamp. its amplitude can be ad- justed. it is also affected by s and c corrections. this positive signal once amplified is to be sent to the crt focusing grids. figure 15. phase of hfocus parabola
TDA9109A 34/47 3 vertical part 3.1 function when the synchronization pulse is not present, an internal current source sets the free running fre- quency. for an external capacitor, c osc = 150nf, the typical free running frequency is 100hz. the typical free running frequency can be calculat- ed by: fo(hz) = 1.5 . 10 -5 . a negative or positive ttl level pulse applied on pin 2 (vsync) as well as a ttl composite sync on pin 1 can synchronize the ramp in the range [fmin, fmax] (see figure 16). this frequency range depends on the external capacitor connected on pin 22. a 150nf ( 5%) capacitor is recommended for 50hz to 185hz applications. if a synchronization pulse is applied, the internal oscillator is synchronized immediately but with wrong amplitude. an internal correction then ad- justs it in less than half a second. the top value of the ramp (pin 22) is sampled on the agc capaci- tor (pin 20) at each clock pulse and a transcon- ductance amplifier modifies the charge current of the capacitor in such a way to make the amplitude constant again. the read status register provides the vertical lock- unlock and the vertical sync polarity information. we recommend the use of an agc capacitor with low leakage current. a value lower than 100na is mandatory. a good stability of the internal closed loop is reached by a 470nf 5% capacitor value on pin 20 (vagc). 3.2 i 2 c control adjustments s and c correction shapes can then be added to this ramp. these frequency-independent s and c corrections are generated internally. their ampli- tudes are adjustable by their respective i 2 c regis- ters. they can also be inhibited by their "select" bits. finally, the amplitude of this s and c corrected ramp can be adjusted by the vertical ramp ampli- tude control register. the adjusted ramp is available on pin 23 (v out ) to drive an external power stage. the gain of this stage can be adjusted ( 25%) de- pending on its register value. the mean value of this ramp is driven by its own i 2 c register (vertical position). its value is vpos = 7/16 . v ref-v 400mv. usually v out is sent through a resistive divider to the inverting input of the booster. since vpos de- rives from v ref-v , the bias voltage sent to the non- inverting input of the booster should also derive from v ref-v to optimize the accuracy (see appli- cation diagram). 3.3 vertical moir by using the vertical moir, vpos can be modulat- ed from frame to frame. this function is intended to cancel the fringes which appear when the line to line interval is very close to the crt vertical pitch. the amplitude of the modulation is controlled by register vmoire on sub-address 0c and can be switched-off via the control bit d8. 1 c osc
TDA9109A 35/47 figure 16. agc loop block diagram 3.4 basic equations in first approximation, the amplitude of the ramp on pin 23 (vout) is: v out - vpos = (v osc - v dcmid ) . (1 + 0.3 (v amp )) where: v dcmid = 7/16 v ref (middle value of the ramp on pin 22, typically 3.6v) v osc = v 22 (ramp with fixed amplitude) v amp = -1 for minimum vertical amplitude register value and +1 for maximum vpos is calculated by: vpos = v dcmid + 0.4 v p where v p = -1 for minimum vertical position regis- ter value and +1 for maximum. the current available on pin 22 is: i osc = . v ref . c osc . f where c osc = capacitor connected on pin 22 and f = synchronization frequency. geometric corrections the principle is represented in figure 17. starting from the vertical ramp, a parabola-shaped current is generated for e/w correction (also known as pin cushion correction), dynamic hori- zontal phase control correction, and vertical dy- namic focus correction. the parabola generator is made by an analog mul- tiplier, the output current of which is equal to: d i = k . ( v out - v dcmid ) 2 where v out is the vertical output ramp (typically between 2 and 5v) and v dcmid is 3.6v (for v ref-v = 8.2v). the vout sawtooth is typical- ly centered on 3.6v. by changing the vertical posi- tion, the sawtooth shifts by 0.4v. to provide good screen geometry for any end user adjustment, the TDA9109A has the geometry tracking feature which allows generation of a dis- symetric parabola depending on the vertical posi- tion. due to the large output stage voltage range (e/w pin cushion, keystone, e/w corner), the combi- nation of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the dac control may lead to output stage saturation. this must be avoided by limiting the output voltage with appropriate i 2 c register values. vsyncin 2 synchro polarity oscillator discharge. 22 osc cap sampling sampling capacitance s correction vs amp sub-add 07/7bits cor_c sub-add 08/7bits c correction 18 breath 23 vout vert. amp sub-.05/7bits vmoir sub.0c/7bits v position sub.06/7bits vlow sawth . disch. ref charge current transconductance amplifier 3 8
TDA9109A 36/47 for the e/w part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: d i = k . ( v out - v dcmid ) then d i and d i are added and converted into volt- age for the e/w part. each of the two e/w components or the two dy- namic horizontal phase control components may be inhibited by their own i 2 c select bit. the e/w parabola is available on pin 24 via an emitter follower output stage which has to be bi- ased by an external resistor (10 k w to ground). since stable in temperature, the device can be dc coupled with external circuitry. the vertical dynamic focus is combined with the horizontal focus on pin 10. the dynamic horizontal phase control drives inter- nally the h-position, moving the hfly position on the horizontal sawtooth in the range of 2.8 %t h both for side pin balance and parallelogram. figure 17. geometric corrections principle 3.5 e/w ewout = ew dc + k1 ( v out - v dcmid ) + k2 ( v out - v dcmid ) 2 + k3 ( v out - v dcmid ) 4 k1 is adjustable by the keystone i 2 c register. k2 is adjustable by the e/w amplitude i 2 c register. k3 is adjustable by the e/w corner i 2 c register. 3.6 dynamic horizontal phase control i out = k4 (v out - v dcmid ) + k5 (v out - v dcmid ) 2 k4 is adjustable by the parallelogram i 2 c register. k5 is adjustable by the side pin balance i 2 c regis- ter.
TDA9109A 37/47 4 dc/dc converter part this unit controls the switch-mode dc/dc con- verter. it converts a dc constant voltage into the b+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. this dc/dc converter can be configured either in step-up or step-down mode. in both cases it oper- ates very similarly to the well known uc3842. 4.1 step-up mode operating description ? the power mos is switched-on during the flyback (at the beginning of the positive slope of the horizontal focus sawtooth). ? the power mos is switched-off when its current reaches a predetermined value. for this purpose, a sense resistor is inserted in its source. the voltage on this resistor is sent to pin16 (i sense ). ? the feedback (coming either from the ehv or from the flyback) is divided to a voltage close to 5.0v and compared to the internal 5.0v reference (i vref ). the difference is amplified by an error amplifier, the output of which controls the power mos switch-off current. main features ? switching synchronized on the horizontal frequency ? b+ voltage always higher than the dc source ? current limited on a pulse-by-pulse basis the dc/dc converter is disabled: ? when v cc or v dd are too low ? when x-ray protection is latched ? directly through i 2 c bus when disabled, bout is driven to gnd by a 0.5ma current source. this feature allows to im- plement externally a soft start circuit. 4.2 step-down mode in step-down mode, the i sense information is not used any more and therefore not sent to the pin16. this mode is selected by connecting pin16 to a dc voltage higher than 6v (for example v ref- v ). operating description ? the power mos is switched-on as for the step-up mode ? the feedback to the error amplifier is done as for the step-up mode ? the power mos is switched-off when the hfocuscap voltage get higher than the error amplifier output voltage main features ? switching synchronized on the horizontal frequency ? b+ voltage always lower than the dc source ? no current limitation 4.3 step-up and step-down mode comparison in step-down mode the control signal is inverted compared with the step-up mode. the reason for this, is the following: ? in step-up mode, the switch is a n-channel mos referenced to ground and made conductive by a high level on its gate. ? in step-down, a high-side switch is necessary. it can be either a p- or a n-channel mos. C for a p-channel mos, the gate is controlled directly from pin 28 through a capacitor (this allows to spare a transformer). in this case, a negative-going pulse is needed to make the mos conductive. therefore it is necessary to invert the control signal. C for a n-channel mos, a transformer is needed to control the gate. the polarity of the transformer can be easily adapted to the neg- ative-going control pulse.
TDA9109A 38/47 figure 18. dc/dc convertor i 2 c dac 7bits 6.2v 5v20% 85db a inhibit soft start s 1/3 1.3v 1.3v c2 c3 8v 6v c4 down up hdf disc 400ns s r q inhibit down up bout 12v TDA9109A regin comp 15 14 16 22k w 1m w ehv feedback v b+ l command step-up/down i sense 28 c1 - + horizontal dynamic focus sawtooth i adjust
TDA9109A 39/47 internal schematics figure 19. figure 20. figure 21. figure 22. figure 23. figure 24. r0 6 12v href 13
TDA9109A 40/47 figure 25. figure 26. figure 27. figure 28. figure 29. figure 30.
TDA9109A 41/47 figure 31. figure 32. figure 33. figure 34. figure 35. figure 36.
TDA9109A 42/47 figure 37. figure 38. figure 39.
TDA9109A 43/47 figure 40. demonstration board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 h/hvin vsyncin hlock out pll2c c0 r0 pll1f h hfocus- cap focus out hgnd hfly href comp regin i sense +5v sda scl v cc b+out gnd hout xray ewout vout v cap v ref vagccap vgnd breath b+gnd position tp1 j11 tp13 tp17 j12 tp16 tp10 c7 22nf c28 820pf 5% r23 (***) c13 10nf c31 4.7 m f r36 c17 470nf c34 820pf 5% href c33 100nf c27 47 m f c46 1nf r50 1m w c51 22 m f jp1 r89 33k w r51 1k w i sense gnd b+out regin c47 100pf r58 10 w +12v c60 100nf r77 15k w r74 10k w r73 1m w r75 10k w tp8 eht comp r76 47k w p1 10k w con4 j19 1 2 3 4 dyn focus r24 10k w l 47m h r25 1k w j9 hfly j8 c22 33pf r8 10k w hout c25 33pf r10 10k w r35 10k w +12v pc2 47k w cc4 47pf +12v cc1 100nf cc2 10 m f +12v cc3 47pf pc1 47k w -12v 1 234 5678 9 10 11 12 13 14 15 16 v cc tb1 tb2 cdb ib qb qb ib ta1 ta2 cda ia ia qa qa gnd icc1 mc1 4528 c50 10 m f l3 22 m h q4 bc557 q5 bc547 c2 100nf c3 47 m f 470nf c15 c12 150nf +12v r52 3.9k w r45 33 k w r7 10 k w c49 100nf hout c48 10 m f r53 1k w +12v r56 560k w d2 1n4148 +12v c5 100 m f c6 100nf c30 100 m f c32 100nf l1 22 m h +5v j16 j15 +5v r39 4.7k w r29 4.7k w r42 100 w j14 1 2 3 4 c39 22pf c40 22pf r41 100 w scl sda c38 33pf c45 10 m f r49 22k w +5v ic3-stv9422 tilt j13 r43 10k w c42 1 m f r30 10k w +5v c43 47 m f c37 33pf x1 8mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pwm4 pwm5 scl sda rst gnd r g b test pwm6 pwm7 pwm3 pwm2 xtalin xtalout ckout pxck v dd hsync vsync fblk pwm1 pwm0 e/w power stage r38 2.2 w 3w j1 e/w r19 270k w c11 220pf q3 tip122 r18 10k w r33 4.7k w r9 470 w r34 1k w q1 bc557 q2 bc557 r37 27k w r15 1k w r17 43k w c36 1 m f +12v j2 j3 j6 1 2 3 j18 vyoke r11 220 w 0.5w r4 1 w 0.5w r5 5.6 w +12v -12v tp3 tp4 tp6 tp7 c9 100nf c14 470 m f c10 100 m f 35v d1 1n4004 -12v c10 470 m f c8 100nf c1 220nf r3 1.5 w c4 100nf r2 5.6k w ic1 tda8172 r40 36k w r1 12k w c41 470pf vertical deflection stage j17 hout c16 (*) ic4 TDA9109A tp14 d10 1n4148 d9 1n4148 d8 1n4148 r90 10k r78 10 w (**) r31 27k (**) (**) (**) (**) see table 9109a 9111 r78 shorted mounted r90 removed mounted r31 mounted removed r17 270k w 43k w r18 39k w 10k w (*) optional +12v tp22 1.8k w (***) for r 23 =6.49k w f 0 =22.8khz typ for r 23 =5.23k w f 0 =28.3khz typ
TDA9109A 44/47 figure 41. pcb layout
TDA9109A 45/47 figure 42. components layout
TDA9109A 46/47 package mechanical data 32 pins - plastic shrink dimensions millimeters inches min. typ. max. min. typ. max. a 3.556 3.759 5.080 0.140 0.148 0.200 a1 0.508 0.020 a2 3.048 3.556 4.572 0.120 0.140 0.180 b 0.356 0.457 0.584 0.014 0.018 0.023 b1 0.762 1.016 1.397 0.030 0.040 0.055 c .203 0.254 0.356 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.906 10.41 11.05 0.390 0.410 0.435 e1 7.620 8.890 9.398 0.300 0.350 0.370 e 1.778 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.540 3.048 3.810 0.100 0.120 0.150 ea eb e1 e d 32 17 16 1 stand-off e b1 b a2 a1 a l c
TDA9109A 47/47 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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